I designed a nibble-oriented CPU in Verilog to build a scientific calculator
The project, by GitHub user gdevic, implements a nibble-oriented CPU in Verilog, targeting an FPGA to create a scientific calculator. The CPU uses a custom 8-bit instruction set with 4-bit nibbles, allowing efficient encoding of operations. The calculator supports functions such as addition, subtraction, multiplication, division, and trigonometric calculations (sine, cosine, tangent) via lookup tables and CORDIC algorithms. The repository includes a complete toolchain: an assembler to convert assembly code to machine code, an emulator for testing, and Verilog source files for synthesis. The design is modular, with separate modules for the ALU, control unit, and I/O. The project was published on May 15, 2026, and is open-source under the MIT license. This work illustrates how custom CPU architectures can be tailored for specific applications, offering insights into computer architecture and FPGA development.
Shows how custom hardware design can optimize for specific tasks like scientific computing.